A 3.3V Single-Poly CMOS Audio ADC Delta-Sigma Modulator with 98dB Peak SINAD

This paper presents a second-order modulator for audio-band A/D conversion implemented in a 3.3V, 0.5 m, single-poly CMOS process that achieves 98dB peak SINAD and over 100dB SFDR. The design uses a reduced-complexity, mismatch-shaping 33-level DAC and a 33-level ash ADC with digital common-mode rejection and dynamic element matching of comparator o sets. These signal processing innovations, combined with established circuit techniques, enable state of the art performance in CMOS optimized for digital circuits. To the knowledge of the authors, this level of performance has not been achieved previously under these process constraints [1], [2], [3]. Introduction The availability of CMOS for implementing inexpensive, high-volume digital circuits makes integrating signal processing systems on a single chip attractive in many situations. The types of functions that can be integrated and the scope of integration are often limited by the ability to perform high resolution data conversion in CMOS optimized for digital circuits. An example of such a system is a high-performance audio processing system where 48 kSample/sec A/D conversion with 98dB SINAD and SFDR is required. Integrating such a converter on a 3.3V, single-poly CMOS process requires overcoming process-induced circuit challenges. Without double-poly or other thin-oxide capacitors, the metal interconnect layers provide the only inherently linear means to implement switched-capacitor circuits. The large bottom plate parasitic capacitance of all-metal capacitors requires high current drive ampli ers. The 3.3V supply limits signal swings necessitating increased sampling capacitances to meet signal to thermal noise requirements. These factors make designing fast-settling, low-distortion integrators a di cult circuit design problem. This paper presents a solution to this problem based on multibit modulation which eases the requirements on the switched-capacitor circuitry. Modulator Multibit quantization in the modulator reduces the quantization noise power that must be shaped out of band relative to single-bit architectures. Thus, the order of the modulator loop lter and the oversampling ratio can be reduced. The simpler loop lter reduces the complexity of the switched-capacitor circuitry, and the lower oversampling ratio eases the integrators' settling time requirements. The reduction in quantization error implies that the maximum step taken by the integrators is reduced, further relaxing the settling requirements. To meet the 98dB SINAD and SFDR targets, the 33level, second-order modulator shown in Fig. 1 was used [4]. It operates at an oversampling ratio of 64 and samples the 0Hz{24kHz input signal at 3.072MHz. With ideal analog components and no DAC element mismatches, it achieves 108dB peak SINAD. Fig. 2 and Fig. 3 show the switched-capacitor implementations of the modulator and feedback DACs, respectively. y[n] x[n] −1 1−z z −1 1−z z